Prednáška prof. Karola Kálnu

ElÚ SAV, v.v.i. pozýva na prednášku Karola Kálnu (Faculty Sci Engn., Swansea Univ., UK). Dňa 27. 6. 2024, 10,00 hod., vo veľkej zasadačke Elektrotechnického ústavu SAV, v.v.i. (miestnosť č. 101), Dúbravská cesta 9, Bratislava
Nanosheet Field-Effect Transistors For The Future Logic Architectures: Process Flow and Performance

Abstrakt:
Nanosheet Field-Effect Transistors emerged as a winning transistor architecture to continue the CMOS technology scaling at and beyond the 3~nm technology node. A fabrication process of stacked n-type gate-all-around (GAA) triple nanosheet (NS) field-effect transistors (FETs) is modelled by the 3D Victory Process (TCAD by Silvaco). The modelling confirms that the NS FET process flow is highly compatible with the FinFET fabrication. The 1st NS channel provides the largest contribution to current density, while additional channels still contribute by a good increase to current density.
The nanosheet (NS) FETs are then scaled to a gate length (Lg) of 16 nm and below and benchmarked against equivalent Nanowire (NW) FETs and FinFETs.  The performance of NS FETs is predicted using a 3D finite element drift-diffusion/Monte Carlo simulation toolbox with integrated 2D Schrödinger equation based quantum corrections. The NS FET is a viable replacement for the FinFET in high performance (HP) applications when scaled down to Lg of 16 nm, offering a larger on-current (I_ON) and slightly better sub-threshold characteristics. Below Lg of 16 nm, the NW FET becomes the most promising architecture, offering an almost ideal sub-threshold swing, the smallest off-current (I_OFF), and the largest I_ON/I_OFF ratio out of the three architectures. Finally, four sources of variability, metal grain granularity (MGG), line-edge roughness (LER), gate-edge roughness (GER), and random discrete dopants (RDD), are analysed. The MGG and LER are shown to be the major sources of variability. The FinFET and the NS FET are similarly affected by the MGG variations, with threshold voltage and on-current standard deviations significantly lower (at least 20 %) than those of the NW FET. The LER variability has a negligible influence in the NS FET performance.